MEMS Logic : From translational 3 layer to torsional 2 Layer

During my 2nd semester, I am doing project on designing NEMS logic that has response less than 10 nsec  using COMSOL which later I will characterize NEMS logic at IMEC (Inter-University Microelectronics Centre – Largest Nanotech research Lab in Europe http://www2.imec.be/be_en/home.html ).

NEMS – Nano Electro Mechanical System logic gates are the NEMS devices that can perform Boolean algebra like the logic gates that are composed of solid state transistors (FET, BJT, etc). The proposed NEMS logic gates are expected to have more applications than NEMS switches and also can be used to construct a full-Mechanical computer. The advantages of this mechanical computer over present days computer are that it can work under severe temperatures and strong ion-radiation environments. Under such conditions, conventional solid state transistors that are used in present days computers fails.

The propose of my project is to design a NEMS logic gate that can be fabricated by Surface micro-machining, which uses same mechanical structure to perform either NAND or NOR gate function depending on the electrical interconnects (just by reversing the voltage polarity, NAND gate switch to NOR gate or vice versa). As we know, it is possible to realize entire digital circuitry by NAND and NOR gate functions, so solely from the proposed NEMS logic gate it has potential application to realize mechanical computer.

But, here I am describing about MEMS logic and later I will describe about NEMS logic design after doing researches at IMEC in the upcoming posts.

Translational 3- Layer Design

It is shown in figure 1., where the device has one shuttle electrode in the middle and two fixed electrode on the top and bottom. When the fixed electrodes are biased at the voltages of Vcc+ and Vcc-, the shuttle electrode moves either up or down, depending on the voltages applied to it.The output terminal is connected to shuttle electrode which can connect to top or bottom electrode and ultimately gives brings the output. Hence, the logic function in this structure is carried by the motion of shuttle electrode. In this logic gate, there are two gaps d1 and d2 which are different in size, d1>d2 whereas two effective areas Aa and Ab are same. Depending on application of bias at Va and Vb, motion of shuttle occurs and thus following four situations occur.

1. Va = Vcc+ and Vb= Vcc- : Here voltage difference between upper half and lower half is same but  d1>d2, upper electrostatic force is smaller than down one. The shuttle electrode moves downward and connects the bottom electrode making the output voltage Vcc+.
2. Va = Vcc- and Vb= Vcc+ : This is the same situation as above so output voltage is Vcc+.
3. Va = Vcc+ and Vb= Vcc+ : Lower half electrostatic force is zero as there is no voltage drop between bottom electrode and shuttle electrode. So, shuttle electrode moves upward connecting the top electrode making output volatge Vcc-.
4. Va = Vcc- and Vb= Vcc- : Upper half electrostatic force is zero as there is no voltage drop between top electrode and shuttle electrode. So, shuttle electrode moves downward connecting the bottom electrode making output volatge Vcc+

Hence this gate performs NAND logic (Vcc+ =logic 1 and Vcc- = logic 0) similar to the logic gate composed of solid state transistors. We can switch this NAND logic gate to NOR logic gate by reversing the bias between top and bottom electrode hence can used same mechanical structure for both NAND and NOR logic gate. This structure has no leakage current which is major advantages over FET logic gate. Also output terminal is always connected to either top or bottom electrode so this design has no undefined state which is an issue in some logic devices composed of solid state transistors. However, due to three layered structure, this design is difficult to fabricate by using Surface micromachining. However, this design can be rotated by 90 degree and fabricated by bulk micro machining.

 

Torsional 2- Layer design

Two layered structure, shown in figure 2, is suitable to fabricate by surface micro-machining which is possible to integrate with existing solid state transistors. Here the shuttle electrode does a see-saw motion which connects the output terminal on each end to export the corresponding output voltage. In three layer design, logic function is controlled by different voltages and different gap whereas in two layer design that is done by different voltages and different dimensions of actuation pad,s Al and Ar.

The actuation torque is always positive for two input signals both at Vcc+ while it is always negative for both input signals at Vcc-. Here micro flexure is designed such that resilient torque remain in between the actuation torque of above both cases. Hence, net torque at (1,1) is always positive and the plate can be actuated from any angle to angle where it connects the output terminal on the right. Similarly, in case (0,0), the plate can be actuated from any angle to angle where it connects the output terminal on the left.

When the input terminals are the combination of either (Vcc+, Vcc-) or (Vcc-, Vcc+) , the plate should be rotated clockwise at any initial angle and then connects the output terminals on the right. Hence, it performs as NOR gate and reversing the voltage polarity at the shuttle electrode it can be switched to NAND gate.