Multigate SOI MOSFETs

The conventional scaling trend for the device, i.e. scaling by reducing device size, is no longer valid for the future generation devices where quantum mechanical effect plays a great role and tunneling and leakage problems will severe the performance of devices. Therefore, scientists are working with different strategies to extend Moore’s Law, such as improving electrostatic control over channel  by means of continued scaling with high K/Metal gate stack and multi gate structures for higher drive current by improving mobility of charge carriers that is done by adopting high mobility channel materials (using Ge or III-V materials) and strain engineering.

Silicon on Insulator transistor has buried oxide layer as soon in figure which plays the main role for providing several advantages. By reducing parasitic drain/source junction capacitances, SOI devices yield improved switching speed and reduced power consumption. By isolating channel from substrate bias effect, it also improves the operating speed. It also provides perfect lateral and vertical isolation from substrate which makes the device free from latch up and inter-device leakage problems.

SOI transistors are of 2 types – PDSOI (partial depleted SOI) and FDSOI ( fully depleted SOI). In PDSOI, silicon film on the BOX layer is thicker than the depletion layer formed beneath the gate oxide, has problems like floating body effects, low threshold voltage variation with temperature as it possess self heating process. This problem has been removed in FDSOI, where silicon film thickness is thin enough or lowly dopes to be fully depleted. However, FDSOI are more sensitive to process variation. One important question is why we are not adopting this properties in present day devices though it has so many several advantages (this ques. was asked by my prof. to me during seminar 😛 ), the reason behind this is the use of FINFET devices which INTEL and TSMC are using in present day devices, which accompanies property like SOI.

In double- gate structure, electric field lines from S/D underneath the device terminate on the bottom of the electrode, and therefore cannot reach the channel region. we can see in the figure that how subthreshold swing has been decreased by the use of double gate structure relative to planar bulk transistor. Double gate structure improves the electrostatic control of gate over channel and no. of equivalent gate is 2 for double gate structure which will provides almost twice drain current than normal planar bulk transistor.

The main advantage of using Multi gate devices is that it supress the drain field much more efficiently. There is a parameter called “Natural length” which  represents length of the region of the channel  that is controlled by drain. Effective gate length should be 5-10 times larger than natural length in order to free from short channel effects. Current drive in Multi Gate FET is equal to current in single gate device times the equivalent no. of gates. So our main purpose is to decrease the natural length parameter. We can see the formula how the natural length parameter depends on dielectric constant of gate oxide and silicon, thickness of silicon and gate oxide. Bu using the no. of equivalent gate, obviously it will decrease the natural length by improving the electrostatic control over channel (i.e. by increasing gate coupling). Also, it proves that how high K material improve the device performance that is obvious by reducing the natural length parameter. In triple gate like pi-Gate and Omega-Gate, equivalent no. of gate is more than 3 (between 3 and 4), hence improve the performance by increasing drain current.

Hence, by using the Multi gate structure in SOI devices, we can improve the performance of transistors by extending Moore’s law and by coupling it with strain engineering, which I discussed in previous section, we can improve mobility of charge carriers much more rapidly, all leads to ultimate high speed of devices.

References:

1. Yong et al, IEEE Vol. 11, No. 3, pp. 93-105, June 25, 2010

2. Colinge et al. Science Direct, Microelectronics engineering 84 (2007) 2071-2076

3. Jurczak et al. IMEC paper, Review of FINFET technology

4. Collaert et al. Solid state electronics 52 (2008) 1291-1296

 

How Intel uses Strain Engineering for Mobility Enhancement

We know that for NMOS transistor, we require tensile strain along channel and  for PMOS, we require compressive strain along channel direction to enhance the mobility of carriers. Due to decrease in dimension of gate length to the few nm scale, short channel effects causes severe degradation in the performance of transistors. Carriers velocity saturates soon which limit the drain current and slow down the devices. Intel got a dramatic performance enhancement in strained channel relative to unstrained one. Intel uses this strain engineering techniques to the transistors having gate length of 45 nm and 50 nm for NMOS and PMOS respectively, accompanied with 1.2 nm gate oxide and Ni salicide. I already mentioned in previous artice that salicide are used to lower the parasitic resistance but here it helps on providing tensile strain along NMOS channel also to enhance the mobility of electrons.

In PMOS, Intel embeds compressively strained SiGe film in the source drain regions by using the selective epitaxial growth process. A combination of compressive SiGe strain and embedded SiGe S/D geometry induces a large uniaxial compressive strain in the channel region, thereby resulting in significant hole mobility improvement. We can see from the figure that on deposition of SiGe film, it produces force laterally which provide stress such that channel length reduces in size providing compressive nature of strain. Such strain causes the change in band structure such that curvature of band increases causing lower in the effective mass of hole and as mobility is inversely proportional to effective mass which ultimately enhance the mobility of hole.

For NMOS, Intel integrate a post salicide “highly-tensile” silicon nitride capping layer due to which the stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drainregions to create tensile strain in NMOS channel. Due to deposition of SiN capping layer, it provide stress to channel region such that it elongates the channel region so called tensile strain which will ultimately change the band structure such that it increases the mobility of electron and hence the performance of NMOS devices.

Hence, the combined techniques of selective SiGe source-drainand high stress silicon nitride capping layer are low cost and highly manufacturable means to induce strain in transistors and allow for separate optimization of PMOS and NMOS devices. Only troublesome to this strain engineering is that we require selective growth process separately for NMOS and PMOS which are core components of CMOS and to integrate them within same substrate is really costly.

References:

[1]. Ghani et al. Intel paper
[2]. K. Rim et al., Symp. VLSI Tech Dig.., pp. 98-99, (2002)
[3]. S. Thompson et al., IEDM Tech Dig., pp. 61-64, (2002)
[4]. S. Ito et al., IEDM Tech Dig., pp. 247-251, (2000)
[5]. A. Shimizu et al., IEDM Tech Dig., pp. 433-437, (2001)