Every people have noticed increase in speed of present technologies, decrease in their price and more slimmer and slimmer devices they are able to use. However, rarely people know about the challenges and complexities scientists are facing just to model a transistor in few nm range and then to fabricate them in chips ultimately by integrating billions of transistors. I have seen how scientists are working on it by sacrificing their entertaining life and totally plunge their life in researches.
Presently we are using Intel chip of 45 nm, this length actually corresponds to dimensions of gate length transistor. More we decrease the size of transistor, classical law fails to follow and ultimately quantum mechanical phenomenon comes into picture. Gate tunneling leakage, Interdevice leakage, scattering phenomenon – all leads to dissipation of power and ultimately accumulation of heat from billions of transistors which ultimately can burn your PC/laptops. Intel, TSMC, these famous companies they are able to fabricate 22 nm transistors and even smaller but the main problem is how to take control over heat accumulation. We can have high performance devices but care must be taken over to reduce power consumption and to control heat production.
These are major problems which we are facing with present planar bulk MOSFET given below.
1.Poor Electrostatics ⇒ Increased Ioff, leakage current from reverse biased diode formed at drain to substrate junction can reach to channel and ultimately make poor electrostatics control over channel.
–Solution: Double Gate, which increases electrostatic control over channel and increase the drain current. Leakage current terminate over lower gate and can’t go to channel region.
2.Poor Channel Transport ⇒ decreased Ion, More we reduce the length of channel, scattering will increase that will saturate the velocity of electrons earlier than saturation drain current.
–Solution – High Mobility Channel /Strain engineering, we can use high mobility channel like Ge on Si epitaxy as we know for Ge, electron mobilty is very high because of its lower effective mass even lower than that of hole. By tensile strain along NMOS channel or compressive strain along PMOS channel, we can increase mobility of charge carriers and ultimately it will increase ON current and hence increase the performance.
3. S/D Parasitic resistance ⇒ decreased Ion current
–Solution – Metal Silicides, as we know silicides have very low resistance and it also improve mobility of charge carriers by providing strain over channel.
4. Gate leakage increased, as thickness of SiO2 goes below 2 nm, tunneling effect comes into picture which causes large leakage current. To increase the speed of transistor, we need to increase Ion for that we need to increase Gate coupling capacitance for which ultimately we need to decrease the thickness of gate oxide.
–Solution – High-K dielectrics – Because of high dielectric, it increases the gate coupling capacitance and we can have thicker gate dielectric between gate and channel that will ultimately improve the performance of device. Nitrided Hafnium silicon oxide have found to be best alternative for high K dielectic.
5.Gate depletion ⇒ increased EOT, because of depletion layer formed between Poly and gate dielectric, additional capacitance is formed in series which ultimately increase the Equivalent oxide thickness(EOT), which is equivalent thickness of gate oxide of gate dielectric that can produce same current, and hence reduce the performance.
–Solution – Metal gate, it prevents the formation of depletion layer so High K- Metal stack is found to be best alternative for poly-gate oxide stack.
Other interesting solutions are Multigate Silicon on Insulator transistor, FINFET, CNT based FET and soon which can overcome present days problems which I will discuss in next chapter in details.
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