Nanotechnology Implementation: CNTFET

Presented on Feb 2009

Carbon nanotubes (CNTs) are nanometer-diameter carbon cylinders consisting of graphene sheet wrapped up to form tube.C-60 allotropes, also called fullerenes are used to make CNT. All carbon atoms are involved in hexagonal aromatic rings only and are therefore in equivalent position, except at the nanotube tips where 6×5 = 30 atoms at each tip are involved in pentagonal rings.

CNT has unique electrical and mechanical properties that it can be shaped to act as conductor, semiconductor and insulator depending on the armchair, chiral and zig-zag structure respectively.

It may be composed of a single shell to form single wall nanotubes (SWNTs) or of several concentric shells to form multi-wall nanotubes (MWNTs).
MWNT was discovered earlier than the latter, which is comprised of 2 to 30 concentric graphitic layers, whose diameter ranges from 10 to 50 nm and more than 10 mm in length.
SWNT, on the other hand, is a lot thinner due to its single graphite layer and has diameter from 1.0 to 1.4 nm.

Single-Walled CNT

Multi-Walled CNT

Comparision of CNT with other

Property	Carbon Nanotubes	Comparatively
Size	0.6-1.8 nm in diameter	Si wires at least 50nm thick
Strength	45 Billion Pascals	Steel alloys have 2 Billion P.
Resilience	Bent and straightened without damage	Metals fracture when bent and restraightened
Conductivity	Estimated at 109 A/cm2	Cu wires burn at 106 A/cm2
Cost	$2500/gram by BuckyUSA in Houston	Gold is $30/gram

Progress of transistor technology

CNTFET features

Main role of CNT as the conducting channel of a MOSFET.

• These new devices are very similar to the CMOS FETs.
• All CNFETs are pFETs by nature.
• nFETs can be made through
  • Annealing
  • Doping
• Very low current and power consumption
• Although tubes are 3nm thick , CNFETs are still the size of the contacts, about 20nm.

Analysis : Transfer Characteristics

•As generally CNT FETs are of p-FET, so the origin of the holes is an important question to address.

•One possibility is that the carrier concentration is inherent to the NT.

•Another possibility is that the majority of carriers are injected at the gold–nanotube contacts. The higher work function of gold leads to the generation of holes in the NT by electron transfer from the NT to the gold electrodes.

Challenges

• CNTs are flexible tubes that can be made conducting or semiconducting.
• Nano-scale, strong and flexible.

Main Challenges are:

• Multilevel interconnects not available
• Chip density still limited to the density of contacts.
• Tube density not entirely exploited
• Fabrication is still a stochastic process
• Alternatives to gold contacts need to be found.

Advantages of CNT FET as Memory

• Great potential for storage memory (116 Gb/cm2 )
• Small size offers faster switching speeds (100GHz ) and low power
• Easy to fabricate: standard semiconductor process
• Bistability gives well defined on & off states
• Nonvolatile nature: no need to refresh.
• Faster than SRAM, denser than DRAM, cheaper than flash memory.
• Have an almost unlimited life, resistant to radiation and magnetism—better than hard drive.

Conclusions

• CMOS technology is approaching saturation – problems in the nanometer range
• Carbon nanotube based FET is one of the best alternative for CMOS technology.

References

• P. Avouris, J, Appenzeller, R.

Martel, And S. Wind, “Carbon nanotube electronics,” P. IEEE, vol. 91, no. 11, pp. 1772-1784, Nov.2003.

• A. Graham, G. Duesberg, W. Hoenlein, F. Kreupl, M. Liebau, R. Martin, B. Rajsekharan, W. Pamler, R. Seidal, W. Steinhoegl, and E. Unger, “ How do carbon nanotubes fit into the semiconductor roadmap?,” Appl.Phys. A, vol. 80, no. 6, pp. 1141-1151, 2005.

• M.P. Anantram and F. Leonard, “Physics of carbon nanotube electronic devices,” Rep. Prog. Phys., vol. 69, no. 3, pp. 507-561, 2006.

•J. B. Cui, et al. “Carbon nanotube memory devices of high charge storage stability”, 2002 Appl. Phys. Lett.

•http://www.photon.t.u-tokyo.ac.jp/~maruyama/agallery/nanotubes

•“Helical microtubules of graphitic carbon”, S. Iijima, Nature 354, 56 (1991)

•http://www.wikipedia.com

•Physics – Springer Handbook of NanoTechnology – B. Bhushan (2003) WW

 

My curiosity towards Nanotech

I was studying B.Tech. electronics engineering at SVNIT college which resides at Surat, Gujarat-India. During the first year of B.tech, I studied about different type of subjects related to all the branches of engineering to have fundamental understanding about all the engineering courses. During these periods we were able to acquire abundant information about latest researches in different engineering sectors.

While I reached second year in SVNIT during my B.tech programme, I started to search about technological advancements. I was so confused about recent devices, which possess much more complicated features and getting more and more miniaturized for as well as  becoming cheaper with time. I got to know that due to reduction in size of transistors, we were able to accommodate large no. of components in a given silicon substrate and thus were able to adjust more functional features and reduced the cost accordingly. Also, due to more competitions among vendors and their compulsion to sell all earlier products after the arrival of newly featured products, companies are compelled to reduce the cost of their products with minimum margin of profit.

Presently most of the technologies are based on silicon and germanium substrate. It was actually the length of gate channel that has been reduced sharply during fabrication process. According to scientists Moore, transistors size will be reduced by half for every 18 months. This means present technologies will reach to 10 nm technology by 2020 and beyond that it seems impossible to capture the market as it can be less reliable and more expensive. Devices with size less than 10 nm operate in ballistic regime which can cause huge leakage current leading to the early failure of devices after few cycles of operation. Still to reach to that level, there are lots of limitations for silicon transistors. More we get compact form of devices, more power will dissipate. This leads to tremendous amount of heat generation which can cause explosion of devices. This is one of the great challenges that present scientists are facing. One of the pragmatic example is our present days laptops which are getting heated immediately than its older version.

When I knew all sorts of limitations that can create barrier for technological advancements, I tried to  google about the alternatives that scientists have found through researches. It was CNT-carbon nanotube based FET which can be really best alternative for present days MOSFET. CNT is a narrow tube having 1 nm diameter which is having strength 1600 times than that of steel and can easily sustain large amopunt of heat generated in the system. CNT can be conductor, semiconductor or insulator depending upon its physical configurations, that is really amazing. CNT is really a boon in the fields of nanotechnology. I also started to read articles about nanotechnology. Use of silver and gold nanoparticles as sensors that can be used for medical purposes has really fascinated me. It really surprises me that how materials changes its physical and chemical properties in nanoparticles form which is totally different from their bulk properties.

I took Nano devices as my electives during 3rd year and knew about different type of nanomaterials, nanosensors, smart sensors and different examples of nano products with working phenomena. Especially in the fields of nanoelectronics, we can have large exposure to do researches to find our own innovative novel products. Large no. of researches have been proposed by different scientists from different international lab houses and still lots of opportunities to create our own innovative designs. As Nanotechnology is a promising fields with multidisciplinary subjects where we need knowledge about biology, chemistry, physics, quantum physics and soon, this provides a real opportunity to exploit all our knowledge that we have gained from school level. Because of this I got more attention towards fields of nanotechnology with full vigor and enthusiasm.

Taking care of my interest, I took “Extreme Ultraviolet Lithography” as my seminar topic that is one of the emerging topic in the fields of nano-fabrications. There are limitations of optical lenses in creating lithography patterns when we go towards lower nm technology. It has successfully replaced by the use of optical mirrors but still number of challenges like making smoothness of mirror, proper focus and soon remain to be properly adjusted. EUV lithography is supposed to be used for the technology below 14 nm. I also learned about the designing of IC layout using IC flow design tool and design architect tool of Mentor Graphics where I reached upto design of SRAM layout but couldn’t completed it properly because of lack of mentor specialized in that work.

Finally I applied to number of renowned Universities in Europe and able to grasp most of the prestigious scholarships like HSP scholarship, TSP scholarship and Erasmus Mundus scholarship. Finally  I decided to go for subjects of interests (Nanoelectronics) rather than Universities ranking and chose KU Leuven as my final destination. I would like to thank my coordinator of KU Leuven for providing me such a wonderful prestigious EU scholarship for pursuing  Master programme in KU Leuven and Chalmers University  🙂